1. Field of the Invention
The present invention relates to semiconductor devices, and more particularly to an assembly comprising a semiconductor chip and a package, especially a chip and a substrate in a wirebond-up ball grid arrays (BGA) and window-BGA packages, with an enhanced thermomechanical reliability.
2. Description of the Prior Art
Thermomechanical reliability of semiconductor devices, especially BGA like wirebond-up BGA or window-BGA packages, is a key element with regard to the overall reliability of such devices. Changes in temperature of the semiconductor devices while in operation bear a big potential of risk due to different materials having different coefficients of thermal expansion (CTE), since they expand differently causing mechanical tensions or mechanical stress whenever different elements consisting of different materials are rigidly attached to one another.
Known packages in their construction are typically based on the mechanical and/or electrical connection of three elements as shown in FIG. 17: A semiconductor chip A, an interposer substrate B with interconnect balls C preferably consisting of solder, and a protection D at least protecting the semiconductor chip A preferably consisting of a polymer. These three elements are usually holohedrally mounted on or with another, that means predominantly connected like glued or molded holohedrally on or with another. Thereby, within the package or housing, a complete and rigid connection within the three elements exists.
Since at least two of these elements, semiconductor chip and substrate, have different thermomechanical properties, especially differing coefficients of thermal expansion (CTE Chip about 3 ppm/K; CTE substrate about 16 ppm/K) with the third element (protection) having thermomechanical properties somewhere in between (CTE protection about 10 ppm/K), however at a temperature change an internal mechanical stress E shown in FIG. 18 results inevitably. The consequences are deflections and distortions of the package inevitably decreasing its reliability. With these regular packages it is not possible to fulfill future reliability requests, for instance >2 kTC −45/120° C. or −45/155° C.
It is a principle object of the present invention to provide a semiconductor device reducing or eliminating thermomechanical tensions or stress resulting in an increased thermomechanical reliability.
In accordance with a first aspect of the present invention, there is provided a semiconductor device, comprising: a substrate for carrying a semiconductor chip on a first surface of said substrate; said semiconductor chip being punctually attached to said substrate on said first surface of said substrate via a single attachment point; and means for protecting said semiconductor chip on said first surface of said substrate at least protecting said semiconductor chip laterally.
According to a second aspect of the present invention, a semiconductor device is provided, comprising: a substrate for indirectly carrying a semiconductor chip via a protection means on a first surface of said substrate, wherein said means for protecting said semiconductor chip is attached to said substrate protecting said semiconductor chip from all sides except the side facing said first surface of said substrate, and said protection means is punctually attached to said semiconductor chip via a single attachment point on the opposite side of said side facing said substrate.
In accordance with a third aspect of the present invention, a semiconductor device is provided, comprising: a substrate having a first coefficient of thermal expansion (CTE) for carrying a semiconductor chip on a first surface of said substrate; said semiconductor chip having a second coefficient of thermal expansion different from said first coefficient of thermal expansion; means for punctually attaching said semiconductor chip to said substrate situated laterally adjacent said semiconductor chip; and means for compensating a different thermal expansion of said substrate and said semiconductor chip at said attachment points, said compensation means having a third coefficient of thermal expansion different from said first and second coefficient of thermal expansion of said substrate and said semiconductor chip, and said compensation means being attached to said semiconductor chip and to said attachment points in between said semiconductor chip and said attachment points.
According to a fourth aspect of the present invention a semiconductor device is described, comprising: a substrate having a first coefficient of thermal expansion (CTE) and a persistent opening for accommodating a semiconductor chip having a second coefficient of thermal expansion within said opening; and a compensations means having a third coefficient of thermal expansion laterally surrounding said semiconductor chip in between said substrate and said semiconductor chip for compensating a different thermal expansion of said substrate and said semiconductor chip.
Thereby, a concept is realized in which the composition of at least two elements, i.e. substrate, semiconductor chip, and preferably protection, is not holohedrally provided. Instead, a connection between the three elements exists only at predetermined attachment points which are thermomechanically neutral. That means that at these attachment points no relative movement of the elements exists at a change of temperature even without attachment. All other points of the three elements can move independently from one another, especially expand or shrink at a temperature change without inducing forces or stresses within the device.
These thermomechanically neutral points can be punctual attachment or connection points between two elements of the composition at predetermined positions. All thermomechanically neutral points are located on compensation lines, i.e. lines where even without attachment no thermally induced relative motion of the chip with respect to the substrate occurs. One or more attachment points can freely be located on such a compensation line.
Thereby a connection or an attachment point is provided at a predetermined location which is selected so that two elements attached to another having different coefficients of thermal expansion seen from a fixed point have the same thermal expansion at that predetermined location as a third material at that point seen from the fixed point at a change of temperature.
If two composition elements are attached with one another via one attachment point only per contact level, that means not laminar, due to a thermally induced expansion, no stress results, since starting from this fixed point, all other volume elements of the contact partners can move freely. If the three elements of the package, i.e. semiconductor chip, substrate, protection, are only attached to one another via these neutral fixed points, it is possible to assemble a stress-free package or housing which does not bend, twist or distort. If a fixed point is set on the front side of a contact element, the respective fixed point on the backside is arranged preferably symmetrically in order to provide a symmetric assembly.
All different aspects of the present invention increase the thermomechanical reliability in that the packages are internally stress-free, i.e. first-level reliability, and in addition are adapted stress-free to the next level of the device architecture, that means second-level reliability. Not every attachment point is necessarily the center of the device. However, the attachment point is preferably situated in the center or near the center within the semiconductor device due to the same amount of expansion in all directions of one level at a change of temperature.
According to a preferred embodiment of the first and second aspect of the present invention as far as said substrate is concerned, said single attachment point is located in or close to the center of said substrate.
According to a further preferred embodiment of the first and second aspect of the present invention as far as said semiconductor chip is concerned, said single attachment point is located in or close to the center of said semiconductor chip.
According to a further preferred embodiment of said first and second aspect of the present invention, said substrate is connected to a carrier, i.e. a circuit board on a second surface of said substrate opposite said first surface via solder, preferably solder bumps, or electrically conductive adhesive.
According to a further preferred embodiment of said first and second aspect of the present invention, said substrate has the same or a comparable coefficient of thermal expansion (CTE) as said carrier.
According to a further preferred embodiment of said first and second aspect of the present invention, said protection means covers said semiconductor chip from all sides except the side facing said first surface of said substrate.
According to a further preferred embodiment of the first and second aspect of the present invention, said protection means is attached to said semiconductor chip punctually via a single attachment point symmetrically to said attachment point between said chip and said substrate. That means that the center position of the chip, the substrate and the protection means respectively and the position of the attachment points of the chip with the substrate and the attachment points of the chip with the protection means is the same respectively.
According to a further preferred embodiment of the first, second and third aspect of the invention, said protection means is spaced apart from said semiconductor chip at least so far that within the entire operation temperature range, preferably about 248 K to 448 K, said semiconductor chip does not touch or apply a force on said protection means.
According to a further preferred embodiment of the first and second aspect of the present invention, in between said substrate and said semiconductor chip a slip agent, preferably silicone, is arranged.
According to a further preferred embodiment of the first, second and third aspect of the present invention, said protection means has the same or a comparable coefficient of thermal expansion (CTE) as said substrate.
According to a further preferred embodiment of the first, second and third aspect of the present invention, said protection means consists of a stainless steel, an alloy, nickel silver or plastics, preferably a polymer.
According to a further preferred embodiment of the first and second aspect of the present invention, said semiconductor chip is electrically connected to a second surface of said substrate through a window, preferably in a center axis of said substrate, in said substrate via bond wires.
According to a further preferred embodiment of the first aspect of the present invention, said protection means is elastic, preferably consisting of a shrunk-on hose, being slidingly arranged on said semiconductor chip.
According to a further preferred embodiment of the first, second and third aspect of the present invention, said punctual attachment is formed by an adhesive, which preferably is epoxy-based.
According to a preferred embodiment of the third aspect of the present invention, said semiconductor chip is punctually attached to said substrate in addition via a single attachment point in or near the center of said semiconductor chip.
According to a further preferred embodiment of the third aspect of the present invention, said compensation means has a predetermined lateral extension, said predetermined lateral extension of said compensation means being selected dependent on the lateral extension of said semiconductor chip from its center and the distance from said center to said lateral attachment points as well as dependent on said third coefficient of thermal expansion.
According to a further preferred embodiment of the third aspect of the present invention, said predetermined lateral extension of said compensation means is determined by multiplying the lateral extension of said semiconductor chip from its center by the difference of the second coefficient of thermal expansion minus the first coefficient of thermal expansion divided by the difference of the first coefficient of thermal expansion minus the third coefficient of thermal expansion.
According to a further preferred embodiment of the third aspect of the present invention, in between said substrate and said semiconductor chip as well as in between said substrate and said compensation means a slip agent, preferably silicone, except at said attachment points, is arranged.
According to a further preferred embodiment of the third aspect of the present invention, said lateral attachment points are equidistant from the center of said semiconductor chip.
According to a further preferred embodiment of the third aspect of the present invention, said lateral attachment points are arranged crosswise or diagonally with respect to said semiconductor chip.
According to a further preferred embodiment of the third aspect of the present invention, said semiconductor chip is located in the center of said substrate.
According to a further preferred embodiment of the third aspect of the present invention, said chip is electrically connected to the first surface of said substrate via bond wires lateral of said semiconductor chip.
According to a further preferred embodiment of the third aspect of the present invention, said compensation means forms a frame surrounding said semiconductor chip laterally.